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A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication.

, , , and . IEEE J. Solid State Circuits, 31 (7): 1063-1066 (1996)

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Leading-zero anticipatory logic for high-speed floating point addition., , , , , and . IEEE J. Solid State Circuits, 31 (8): 1157-1164 (1996)A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication., , , and . IEEE J. Solid State Circuits, 31 (7): 1063-1066 (1996)A 286 MHz 64-b floating point multiplier with enhanced CG operation., , , , , and . IEEE J. Solid State Circuits, 31 (4): 504-513 (1996)A 1.9-GHz single chip IF transceiver for digital cordless phones., , , , , , , and . IEEE J. Solid State Circuits, 31 (12): 1974-1980 (1996)A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode., , , , , , , , and . IEEE J. Solid State Circuits, 32 (7): 1101-1107 (1997)A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search., , , , , , , , , and . IEEE J. Solid State Circuits, 30 (12): 1502-1509 (December 1995)Comments on "Leading-zero anticipatory logic for high-speed floating point addition" with reply., , , , , , and . IEEE J. Solid State Circuits, 32 (2): 292 (1997)