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Disambiguation of "Kim, Wooseok"

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A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.

, , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1834-1838 (2020)

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Ky ng Kim

Die Artikelstruktur in passiven zweisprachigen Wörterbüchern Deutsch-Koreanisch: Konzeption zur Erstellung eines zweisprachigen Lernerwörterbuchs Deutsch-Koreanisch. Uni Heidelberg, (2008)

Bongcheol Kim

Youngsang Kim

Sunghun Kim

Taekwan Kim

 

Other publications of authors with the same name

A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology., , , , , and . ISSCC, page 120-122. IEEE, (2018)A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology., , , , , and . CICC, page 1-4. IEEE, (2014)A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS., , , , , and . BCICTS, page 263-266. IEEE, (2018)Utilization of Artifact and Noise Affected Electrocardiogram for Simultaneous Heart Rate Computation and Motion Type Inference., , , , , , , , , and 1 other author(s). SENSORS, page 1-4. IEEE, (2023)Anticipatory transport system with hybrid linear and nonlinear forecasting using streaming wafer process data., , , , , and . Appl. Soft Comput., (2022)A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to-Current Converter., , , , , , , , , and 1 other author(s). ISSCC, page 310-605. IEEE, (2007)"I Can't Talk Now": Speaking with Voice Output Communication Aid Using Text-to-Speech Synthesis During Multiparty Video Conference., and . CHI Extended Abstracts, page 288:1-288:6. ACM, (2021)TaleBrush: Visual Sketching of Story Generation with Pretrained Language Models., , , , , and . CHI Extended Abstracts, page 172:1-172:4. ACM, (2022)14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology., , , , , and . ISSCC, page 1-3. IEEE, (2015)Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator., , , and . IEEE J. Solid State Circuits, 49 (3): 657-672 (2014)