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Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection.

X. Wang, X. Wang, F. Lu, C. Zhang, Z. Dong, L. Wang, R. Ma, Z. Shi, A. Wang, M. Chang, D. Wang, A. Joseph, and C. Yue. IEEE J. Solid State Circuits, 49 (9): 1927-1941 (2014)

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Z Taufig

Wang Wang

Bence Z Szalai

Leonardo Quevedo Z

Milorad Z Djordjevic

Other publications of authors with the same name

A Varying Pulse Width Second Order Derivative Gaussian Pulse Generator for UWB Transceivers in CMOS.H. Xie, X. Wang, A. Wang, B. Qin, H. Chen, Y. Zhou, and B. Zhao. ISCAS, page 2794-2797. IEEE, (2007)ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism.R. Zhan, H. Feng, Q. Wu, H. Xie, X. Guan, G. Chen, and A. Wang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (10): 1421-1428 (2004)A design technique overview on broadband RF ESD protection circuit designs.L. Wang, R. Ma, A. Wang, X. Wang, B. Zhao, X. Wang, P. Yue, Z. Shi, and Y. Cheng. MWSCAS, page 590-593. IEEE, (2012)Integrated stacked-Spiral RF inductor with nanopowder magnetic Core.J. Zhang, C. Yang, X. Wang, T. Ren, A. Wang, Y. Yang, and L. Tian. J. Circuits Syst. Comput., (2013)ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress.R. Zhan, H. Xie, H. Feng, and A. Wang. ASP-DAC, page 79-82. ACM Press, (2005)A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS.C. Wang, F. Zhang, F. Lu, Q. Chen, C. Li, and A. Wang. IEEE Access, (2020)Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection.X. Wang, X. Wang, F. Lu, C. Zhang, Z. Dong, L. Wang, R. Ma, Z. Shi, A. Wang, M. Chang and 3 other author(s). IEEE J. Solid State Circuits, 49 (9): 1927-1941 (2014)Visible Light Communication Cyber-Physical Systems-on- Chip for Smart Cities.Z. Pan, T. Lang, C. Li, M. Di, G. Chen, Y. Kalay, R. Pai, and A. Wang. J. Commun., 14 (12): 1141-1146 (2019)Introduction to the Special Section on the 2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.A. Wang. IEEE J. Solid State Circuits, 49 (9): 1875 (2014)Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS.J. Liu, X. Wang, H. Zhao, Q. Fang, A. Wang, L. Lin, H. Tang, S. Fan, B. Zhao, S. Wen and 1 other author(s). IEEE J. Solid State Circuits, 46 (5): 1100-1110 (2011)

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Disambiguation of "Wang, Albert Z."

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Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection.

Please choose a person to relate this publication to

Z Taufig

Wang Wang

Bence Z Szalai

Leonardo Quevedo Z

Milorad Z Djordjevic

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Albert Z."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection.

Please choose a person to relate this publication to

Z Taufig

Wang Wang

Bence Z Szalai

Leonardo Quevedo Z

Milorad Z Djordjevic

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection.