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Disambiguation of "Palaniveloo, Vinitha Arakkonam"

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Improving GA-Based NoC Mapping Algorithms Using a Formal Model.

, , and . ISVLSI, page 344-349. IEEE Computer Society, (2014)

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Other publications of authors with the same name

System level modeling and verification of NoC components using model checking.. University of New South Wales, Sydney, Australia, (2014)base-search.net (ftunswworks:oai:unsworks.unsw.edu.au:1959.4/54268).Application of Formal Methods for System-Level Verification of Network on Chip., and . ISVLSI, page 162-169. IEEE Computer Society, (2011)Improving GA-Based NoC Mapping Algorithms Using a Formal Model., , and . ISVLSI, page 344-349. IEEE Computer Society, (2014)Formal Estimation of Worst-Case Communication Latency in a Network-on-Chip., and . ISVLSI, page 15-20. IEEE Computer Society, (2012)