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Другие публикации лиц с тем же именем

Low Complexity SST Viterbi Decoder., и . VTC Fall, стр. 1-2. IEEE, (2006)A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture., , , , и . CODES+ISSS, стр. 161-170. ACM, (2012)A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications., и . ISLPED, стр. 406-411. ACM, (2006)A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes., , и . ISCAS, стр. 1-5. IEEE, (2019)An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms., , , , , и . NOCS, стр. 17-24. IEEE, (2014)Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO., и . VLSI-SoC, стр. 1-5. IEEE, (2016)A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources., , и . VLSI-SoC, стр. 192-195. IEEE, (2011)A thermal-aware application specific routing algorithm for Network-on-Chip design., и . ASP-DAC, стр. 449-454. IEEE, (2011)The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control., , и . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1138-1142 (2009)An Energy Efficient Layered Decoding Architecture for LDPC Decoder., и . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1185-1195 (2010)