( en | de | ru )

 

Disambiguation of "Acle, Julio Pérez"

Author of the publication

copydeleteadd this publication to your clipboard
NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices.

, , , , and . DATE, page 218-223. IEEE Computer Society, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Julio César Pastrana Pérez

Ema Pérez Bravo

Roberto Francisco Pérez Benito

José Guadalupe Pérez-Ramírez

Elsa Pérez Rodriguez

 

Other publications of authors with the same name

On the functional test of the cache coherency logic in multi-core systems., , , and . LASCAS, page 1-4. IEEE, (2015)Analysis and implementation of low-cost FPGA-based digital pulse-width modulators., , , and . I2MTC, page 1523-1528. IEEE, (2014)Fault Tolerant Architecture Design of a CubeSat Command and Data Handling System., , , , , , , and . LATS, page 1-6. IEEE, (2023)Auxiliary IP blocks for early dependability analysis of small processor based systems., , and . LATS, page 21-26. IEEE, (2016)Validation of the dependability of CAN-based networked systems., , , , and . HLDVT, page 161-164. IEEE Computer Society, (2004)A multi-level approach to the dependability analysis of networked systems based on the CAN protocol., , , and . SBCCI, page 71-75. ACM, (2004)NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices., , , , and . DATE, page 218-223. IEEE Computer Society, (2004)About Performance Faults in Microprocessor Core in-field Testing., , and . LASCAS, page 229-232. IEEE, (2019)FPGA-controlled PCBA power-on self-test using processor's debug features., , , , and . DDECS, page 125-130. IEEE, (2016)