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A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.

C. Cheng, J. Wang, P. Chou, S. Chen, C. Sun, Y. Chu, and T. Yang. A-SSCC, page 361-364. IEEE, (2014)

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Yi Yang

Yi-Tzu Lu

Other publications of authors with the same name

A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process.Z. Luo, M. Ker, T. Yang, and W. Cheng. IEEE Trans. Biomed. Circuits Syst., 11 (5): 1087-1096 (2017)SiGe Class-E Power Amplifier with Envelope Tracking for Mobile WiMAX/Wibro Applications.Y. Li, J. Lopez, D. Lie, K. Chen, S. Wu, and T. Yang. ISCAS, page 2017-2020. IEEE, (2009)A 14-band Frequency Synthesizer for MB-OFDM UWB Application.C. Liang, S. Liu, Y. Chen, T. Yang, and G. Ma. ISSCC, page 428-437. IEEE, (2006)SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration.P. Huang, S. Hsien, V. Lu, P. Wan, S. Lee, W. Liu, B. Chen, Y. Lee, W. Chen, T. Yang and 2 other author(s). CICC, page 1-4. IEEE, (2010)A Novel Multifunction CFOA-Based Inverse Filter.H. Wang, S. Chang, T. Yang, and P. Tsai. Circuits and Systems, 2 (1): 14-17 (2011)SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration.P. Huang, S. Hsien, V. Lu, P. Wan, S. Lee, W. Liu, B. Chen, Y. Lee, W. Chen, T. Yang and 2 other author(s). IEEE J. Solid State Circuits, 46 (8): 1893-1903 (2011)A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.C. Cheng, J. Wang, P. Chou, S. Chen, C. Sun, Y. Chu, and T. Yang. A-SSCC, page 361-364. IEEE, (2014)Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem.X. Qian, Y. Wu, T. Yang, C. Cheng, H. Chu, W. Cheng, T. Yen, T. Lin, Y. Lin, Y. Lee and 13 other author(s). IEEE Trans. Biomed. Eng., 66 (11): 3156-3167 (2019)Efficient Deployment of UWB Anchors for Wide-Area Positioning Coverage Using Bipartite Graph.T. Yang, M. Yu, and R. Wu. IEEE Access, (2023)An ultra-low power interface CMOS IC design for biosensor applications.W. Hu, Y. Liu, V. Das, C. Schecht, T. Nguyen, D. Lie, T. Yan, C. Kuo, S. Wu, Y. Chu and 1 other author(s). MWSCAS, page 1196-1199. IEEE, (2012)

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Disambiguation of "Yang, Tzu-Yi"

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A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.

Please choose a person to relate this publication to

Yi Yang

Yi Yang

Yi Yang

Yi Yang

Yi-Tzu Lu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, Tzu-Yi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.

Please choose a person to relate this publication to

Yi Yang

Yi Yang

Yi Yang

Yi Yang

Yi-Tzu Lu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.