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Disambiguation of "Karanth, Avinash"

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Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs.

, , and . ACM J. Emerg. Technol. Comput. Syst., 15 (1): 4:1-4:16 (2019)

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Avinash Vyas

Avinash Sudhodanan

Avinash Sidhu

Avinash Burla

Avinash Sonawane

 

Other publications of authors with the same name

Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 3638-3649 (2020)SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference., , and . HPCA, page 831-845. IEEE, (2022)4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs., , , and . ICECS, page 1-4. IEEE, (2020)Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects., , and . DAC, page 931-936. IEEE, (2021)Exploiting Wireless Technology for Energy-Efficient Accelerators With Multiple Dataflows and Precision., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (7): 2742-2755 (2022)CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters., , , and . HPCA, page 612-625. IEEE, (2021)Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs., , and . ACM J. Emerg. Technol. Comput. Syst., 15 (1): 4:1-4:16 (2019)Guest Editors' Introduction to the Special Issue on Machine Learning Architectures and Accelerators., , and . IEEE Trans. Computers, 69 (7): 929-930 (2020)HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip Architecture., and . IEEE Trans. Emerg. Top. Comput., 10 (2): 537-548 (2022)A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration., , and . IEEE Trans. Parallel Distributed Syst., 35 (1): 46-58 (January 2024)