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Disambiguation of "Wong, Martin D. F."

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L2O-ILT: Learning to Optimize Inverse Lithography Techniques.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (3): 944-955 (March 2024)

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Alexander D F Lahmann

Blaise F D Bourgeois

Walter Wong

Martin F Almstetter

martin f. hellwig

 

Other publications of authors with the same name

Layout Decomposition for Multiple Patterning., and . Encyclopedia of Algorithms, (2016)Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach., and . Encyclopedia of Algorithms, Springer, (2008)Circuit clustering for delay minimization under area and pin constraints., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 976-986 (1997)Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (1): 63-71 (2002)On shifting blocks and terminals to minimize channel density., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (2): 178-186 (1994)GAMER: GPU-Accelerated Maze Routing., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 583-593 (February 2023)PolyPUF: Physically Secure Self-Divergence., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (7): 1053-1066 (2016)Optimal floorplan area optimization., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (8): 992-1002 (1992)CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (10): 3402-3411 (October 2023)BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (11): 1679-1690 (2009)