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EDA challenges and options: investing for the future., , , , , , and . DAC, page 1-2. ACM, (2010)Developing Parallel EDA Tools The Last Byte.. IEEE Des. Test, 30 (1): 65-66 (2013)Combinatorial cell design for CMOS libraries., , , , and . Integr., 29 (1): 67-93 (2000)False loops through resource sharing.. ICCAD, page 345-348. IEEE Computer Society / ACM, (1992)The Next 25 Years in EDA: A Cloudy Future?. IEEE Des. Test, 31 (2): 40-46 (2014)BooleDozer: Logic synthesis for ASICs., , , , , , , , , and . IBM J. Res. Dev., 40 (4): 407-430 (1996)Variability and New Design Paradigms.. IEEE Des. Test Comput., 25 (4): 344 (2008)From restrictive to prescriptive design.. ASP-DAC, IEEE, (2009)Foreground memory management in data path synthesis., and . I. J. Circuit Theory and Applications, 20 (3): 235-255 (1992)Is high-level synthesis marketable? (panel).. HLSS, page 66. ACM, (1994)