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A fully-integrated 130nm CMOS DC-DC step-down converter, regulated by a constant on/off-time control system.

, and . ESSCIRC, page 62-65. IEEE, (2008)

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Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies., , , and . DAC, page 944-947. IEEE, (2007)Energy Supply and ULP Detection Circuits for an RFID Localization System in 130 nm CMOS., and . IEEE J. Solid State Circuits, 45 (7): 1273-1285 (2010)Fully Integrated Wide Input Voltage Range Capacitive DC-DC Converters: The Folding Dickson Converter., and . IEEE J. Solid State Circuits, 50 (7): 1560-1570 (2015)CYCLONE: automated design and layout of RF LC-oscillators., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (10): 1161-1170 (2002)Low-voltage Analog CMOS Filter Design., , , and . ISCAS, page 1447-1450. IEEE, (1993)A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications., , and . ISCAS, IEEE, (2006)Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard., , , , and . DAC, page 25-30. ACM, (2006)A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM., and . ESSCIRC, page 295-298. IEEE, (2004)Digital communication systems: the problem of analog interface circuits., , , , and . ESSCIRC, page 423-426. IEEE, (2005)A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS., , , and . ESSCIRC, page 336-339. IEEE, (2009)