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Robust tests for parity trees., and . J. Electron. Test., 1 (3): 191-200 (1990)Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime., and . IET Circuits Devices Syst., 6 (5): 355-365 (2012)Game theoretic approach for run-time task scheduling on an multi-processor system on chip., and . IET Circuits Devices Syst., 7 (5): 243-252 (2013)MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs., , and . CoRR, (2020)Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (1): 155-165 (2016)Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units., , and . IEEE Trans. Computers, 53 (1): 83-88 (2004)A guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUF., , and . ISCAS, page 1-4. IEEE, (2017)Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing., , , and . ACM Trans. Design Autom. Electr. Syst., 18 (1): 5:1-5:23 (2012)Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance., , , , and . CF, page 54-61. ACM, (2018)A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency., , , , and . PACT, page 491-492. ACM, (2014)