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Disambiguation of "Vasantha, M. H."

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Low power, high speed error tolerant multiplier using approximate adders.

, , , and . VDAT, page 1-6. IEEE Computer Society, (2015)

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Gernot H M Günther

Gesa H -M Bertrang

Philippe H M Bräunig

H J M Turner

Gernot H M Günther

 

Other publications of authors with the same name

A 0.5 V Low Power DTMOS OTA-C Filter for ECG Sensing Applications., , , , and . IEEE SENSORS, page 1-4. IEEE, (2018)Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications., , , , and . Integr., (2021)Two-Step Flash ADC Using Standard Cell Based Flash ADCs., , , , and . iSES, page 292-295. IEEE, (2019)Design and Analysis of Energy Efficient Reversible Logic based Full Adder., , , , and . MWSCAS, page 339-342. IEEE, (2019)Reversible Logic Implementation of Image Denoising for Grayscale Images., , , and . MWSCAS, page 138-141. IEEE, (2020)Approximate Three-Operand Binary Adder for Error-Resilient Applications., , , , and . iSES, page 287-291. IEEE, (2023)Performance Enhancement of Split Length Compensated Operational Amplifiers., , , and . ISVLSI, page 608-613. IEEE Computer Society, (2018)Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing., , , and . ISVLSI, page 585-588. IEEE Computer Society, (2017)An Asynchronous Analog to Digital Converter for Surveillance Camera Applications., , , , and . ISVLSI, page 164-169. IEEE Computer Society, (2018)A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core., , and . ISVLSI, page 146-151. IEEE Computer Society, (2016)