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Disambiguation of "Cline, Brian"

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System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 888-898 (2019)

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Brandon Cline

Rolf-Walter Briant

Benoît Briand

Ursula Brian

Annette Brians

 

Other publications of authors with the same name

Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability., , , , , , , , and . DAC, page 76:1-76:6. ACM, (2016)Standard Cell Library Design and Optimization Methodology for ASAP7 PDK., , , , , and . CoRR, (2018)Mechanical Stress Aware Optimization for Leakage Power Reduction., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (5): 722-736 (2010)Monolithic 3D IC design: Power, performance, and area impact at 7nm., , , , , , , and . ISQED, page 41-48. IEEE, (2016)Transistor-Specific Delay Modeling for SSTA., , , , and . DATE, page 592-597. ACM, (2008)STEEL: a technique for stress-enhanced standard cell library design., , , and . ICCAD, page 691-697. IEEE Computer Society, (2008)Design benchmarking to 7nm with FinFET predictive technology models., , , , and . ISLPED, page 15-20. ACM, (2012)Self-aligned double patterning aware pin access and standard cell layout co-optimization., , , , and . ISPD, page 101-108. ACM, (2014)Exploring Variability and Performance in a Sub-200-mV Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 43 (4): 881-891 (2008)The past present and future of design-technology co-optimization., , , , , and . CICC, page 1-8. IEEE, (2013)