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Disambiguation of "Jou, Jing-Yang"

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Layout techniques for on-chip interconnect inductance reduction.

, , and . ASP-DAC, page 269-273. IEEE Computer Society, (2004)

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Jing Yang

Jing-Mao Yang

Nabil Al-Jou Jou

Yuanyuan Jing

Guangmei Jing

 

Other publications of authors with the same name

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping., , , , , , , , , and 1 other author(s). SoCC, page 137-140. IEEE, (2006)An automorphic approach to verification pattern generation for SoC design verification using port-order fault model., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (10): 1225-1232 (2002)Expandable MDC-based FFT architecture and its generator for high-performance applications., , , and . SoCC, page 188-192. IEEE, (2010)An observability measure to enhance statement coverage metric for proper evaluation of verification completeness., , and . ASP-DAC, page 323-326. ACM Press, (2005)A read-write aware DRAM scheduling for power reduction in multi-core systems., , , and . ASP-DAC, page 604-609. IEEE, (2014)A power driven two-level logic optimizer., and . ASP-DAC, page 113-116. IEEE, (1997)A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication., , , and . ASP-DAC, page 600-605. IEEE, (2006)An efficient logic extraction algorithm using partitioning and circuit encoding., , , and . ISCAS (5), page 249-252. IEEE, (2004)OPAM: an efficient output phase assignment for multilevel logic minimization., , and . ICCD, page 270-273. IEEE, (1989)1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method., , , and . ASP-DAC, page 469-474. ACM, (2021)