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A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects., , , , and . Nano-Net, page 1-6. IEEE, (2006)A quadtree communication structure for fast data searching and distribution., , and . COMPSAC, page 316-323. IEEE, (1988)Providing fairness in DiffServ architecture., , , and . GLOBECOM, page 1435-1439. IEEE, (2002)CASH: compiler assisted hardware design for improving DRAM energy efficiency in CNN inference., , , , , and . MEMSYS, page 396-407. ACM, (2019)Leveraging value locality for efficient design of a hybrid cache in multicore processors., , , and . ICCAD, page 1-8. IEEE, (2017)A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers., and . IEEE Trans. Computers, 51 (1): 46-60 (2002)article no. PC981515, , , , , , , , , and 1 other author(s). journal of parallel and distributed computing, (1998)Optimizing energy consumption in GPUS through feedback-driven CTA scheduling., , , and . SpringSim (HPC), page 12:1-12:12. ACM, (2017)Hybrid-comp: A criticality-aware compressed last-level cache., , , and . ISQED, page 25-30. IEEE, (2018)Editorial to special section on networks on chip: Architecture, tools, and methodologies., and . ACM Trans. Design Autom. Electr. Syst., 18 (4): 45:1-45:2 (2013)