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High-speed multioperand addition and subtraction using a p-ary representation with necessary and minimum redundancy.. Syst. Comput. Jpn., 20 (4): 59-70 (1989)High speed IDDQ test and its testability for process variation., , , , and . Asian Test Symposium, page 344-349. IEEE Computer Society, (2000)Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field., , , , and . DFT, page 287-. IEEE Computer Society, (2001)Fault Detection of Combinational Circuits Based on Supply Current., , , and . ITC, page 374-380. IEEE Computer Society, (1988)Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits., , and . IEICE Trans. Inf. Syst., 87-D (3): 571-579 (2004)Identification of Feedback Bridging Faults with Oscillation., , and . Asian Test Symposium, page 25-. IEEE Computer Society, (1999)Test Time Reduction for I DDQ Testing by Arranging Test Vectors., , and . Asian Test Symposium, page 423-428. IEEE Computer Society, (2002)Practical Fault Coverage of Supply Current Tests for Bipolar ICs., , , and . DELTA, page 189-194. IEEE Computer Society, (2004)A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified Machines., , and . ISCAS, page 193-196. IEEE, (1994)Electric field for detecting open leads in CMOS logic circuits by supply current testing., , , and . ISCAS (3), page 2995-2998. IEEE, (2005)