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Disambiguation of "Bainbridge, John"

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Adding Testability to an Asynchronous Interconnect for GALS SoC.

, , and . Asian Test Symposium, page 20-23. IEEE Computer Society, (2004)

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Walter John

Annemarie Johne

Walter John

Ingeborg John

Hans-Dieter John

 

Other publications of authors with the same name

Defining Testability Metrics Axiomatically.. Softw. Test. Verification Reliab., 4 (2): 63-80 (1994)A Heuristic Method for Generating Large Random Expressions.. Inf. Process. Lett., 44 (3): 165-170 (1992)Sparse distributed memory using N-of-M codes., , , and . Neural Networks, 17 (10): 1437-1451 (2004)Chain: A Delay-Insensitive Chip Area Interconnect., and . IEEE Micro, 22 (5): 16-23 (2002)Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (12): 1384-1393 (2005)Future Trends in SoC Interconnect., and . SoC, IEEE, (2005)Obtaining Structural Metrics of Z Specifications for Systems Development., , and . Z User Workshop, page 269-281. Springer, (1990)Adding Testability to an Asynchronous Interconnect for GALS SoC., , and . Asian Test Symposium, page 20-23. IEEE Computer Society, (2004)Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus., , , , , , , and . ASYNC, page 60-72. IEEE Computer Society, (2007)Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links., and . ASYNC, page 35-44. IEEE Computer Society, (2009)