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Dynamic Path Reduction for Software Model Checking.

, , , , , and . IFM, volume 5423 of Lecture Notes in Computer Science, page 322-336. Springer, (2009)

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The Aurora RAM Compiler., , , , and . DAC, page 261-266. ACM Press, (1995)Analysis and Design of Latch-Controlled Synchronous Digital Circuits., , and . DAC, page 111-117. IEEE Computer Society Press, (1990)Incorporating user control in automated interactive scheduling systems., , , , and . Conference on Designing Interactive Systems, page 306-309. ACM, (2010)Transistor placement for noncomplementary digital VLSI cell synthesis., and . ACM Trans. Design Autom. Electr. Syst., 8 (1): 81-107 (2003)Dynamic symmetry-breaking for improved Boolean optimization., , , and . ASP-DAC, page 445-450. ACM Press, (2005)Concurrent path sensitization in timing analysis., and . EURO-DAC, page 196-199. IEEE Computer Society, (1993)A first-order charge conserving MOS capacitance model., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (1): 99-108 (1990)Critical paths in circuits with level-sensitive latches., , and . IEEE Trans. Very Large Scale Integr. Syst., 3 (2): 273-291 (1995)euforia: Complete Software Model Checking with Uninterpreted Functions., and . VMCAI, volume 11388 of Lecture Notes in Computer Science, page 363-385. Springer, (2019)Empirical Study of the Anatomy of Modern Sat Solvers., , and . SAT, volume 6695 of Lecture Notes in Computer Science, page 343-356. Springer, (2011)