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29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS., , , , , , , and . ISSCC, page 492-493. IEEE, (2017)8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS., , , , and . ISSCC, page 152-153. IEEE, (2017)A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS., , , , , and . ISSCC, page 392-394. IEEE, (2018)A 3.2-GHz 405 fsrms Jitter -237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer., , , , , and . IEEE J. Solid State Circuits, 57 (3): 698-708 (2022)A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction., , , , , and . CICC, page 1-2. IEEE, (2021)A 0.7V time-based inductor for fully integrated low bandwidth filter applications., , , , , , and . CICC, page 1-4. IEEE, (2017)A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 53 (2): 445-457 (2018)Circuits for time-domain signal processing. University of Illinois Urbana-Champaign, USA, (2020)A self-clocked ASIC interface for MEMS gyroscope with 1m°/s/√Hz noise floor., , , , , , , , , and 12 other author(s). CICC, page 1-4. IEEE, (2011)A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier., , , and . IEEE J. Solid State Circuits, 53 (6): 1818-1829 (2018)