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PASTA: Partial Scan to Enhance Test Compaction.

, and . Great Lakes Symposium on VLSI, page 4-7. IEEE Computer Society, (1999)

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Random error and burst correction by iterated codes., and . IEEE Trans. Inf. Theory, 18 (1): 182-185 (1972)Random Test Generation With Input Cube Avoidance., and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 45-54 (2009)Path Selection for Transition Path Delay Faults., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (3): 401-409 (2010)Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units., and . IEEE Trans. Very Large Scale Integr. Syst., 9 (5): 679-689 (2001)A Repair-for-Diagnosis Methodology for Logic Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (11): 2254-2267 (2018)Universal delay test sets for logic networks., , and . IEEE Trans. Very Large Scale Integr. Syst., 7 (2): 156-166 (1999)Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes., and . IEEE Trans. Computers, 25 (9): 945-949 (1976)On the Design of Testable Domino PLAs., and . ITC, page 567-573. IEEE Computer Society, (1985)Test Generation for Multiple State-Table Faults in Finite-State Machines., and . IEEE Trans. Computers, 46 (7): 783-794 (1997)On the Design of Pseudoexhaustive Testable PLA's., and . IEEE Trans. Computers, 37 (4): 468-472 (1988)