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Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks.

, , and . FPT, page 145-152. IEEE, (2004)

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Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures., and . FPL, page 1-6. IEEE, (2006)Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1113-1115. Springer, (2004)Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks., , and . FPT, page 145-152. IEEE, (2004)Exploiting parallelism in configurable architectures through custom array mapping., and . IET Comput. Digit. Tech., 1 (4): 303-311 (2007)Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-Level Synthesis., and . FPT, page 233-240. IEEE, (2005)A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures, and . CoRR, (2007)Extending the Applicability of Scalar Replacement to Multiple Induction Variables., , and . LCPC, volume 3602 of Lecture Notes in Computer Science, page 455-469. Springer, (2004)A compiler approach to managing storage and memory bandwidth in configurable architectures., and . ACM Trans. Design Autom. Electr. Syst., 13 (4): 61:1-61:26 (2008)A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures., and . DATE, page 6-11. IEEE Computer Society, (2005)