( en | de | ru )

 

Disambiguation of "Yu, Shimeng"

Author of the publication

copydeleteadd this publication to your clipboard
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.

, , , , , and . DATE, page 1423-1428. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shimeng Chen

Yu-Ting Yu

Yu-Yu Su

Sze-Man Yu

Metal complexes with enolatoimine ligands for controlled olefin polymerizations. Uni Konstanz, (2009)

Zhejun Yu

 

Other publications of authors with the same name

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain., , , , , , , , , and 5 other author(s). CoRR, (2018)Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2205-2212 (2019)H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (10): 1592-1602 (October 2023)Three-Dimensional nand Flash for Vector-Matrix Multiplication., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 988-991 (2019)Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (10): 2962-2965 (2017)Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (12): 2027-2039 (2021)Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (2): 386-396 (2021)Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1683-1689 (March 2024)Compute-in-Memory for AI: From Inference to Training.. VLSI-DAT, page 1. IEEE, (2020)Improving efficiency in sparse learning with the feedforward inhibitory motif., , , , , , , and . Neurocomputing, (2017)