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PDES-A: a Parallel Discrete Event Simulation Accelerator for FPGAs.

, , and . SIGSIM-PADS, page 133-144. ACM, (2017)

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Compiled hardware acceleration of Molecular Dynamics code., and . FPL, page 667-670. IEEE, (2008)Conditional Disconnection Probability in Star Graphs., and . VLSI Design, 1 (1): 61-70 (1993)Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads., , , , , and . ACM Trans. Archit. Code Optim., 16 (2): 13:1-13:28 (2019)A way-halting cache for low-energy high-performance systems., , , and . ACM Trans. Archit. Code Optim., 2 (1): 34-54 (2005)Compile-time area estimation for LUT-based FPGAs., , , and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 104-122 (2006)Reconfigurable Computing in the New Age of Parallelism., and . SAMOS, volume 5657 of Lecture Notes in Computer Science, page 255-262. Springer, (2009)Preliminary Evaluation of a Hybrid Deterministic/Adaptive Router., and . PCRCW, volume 1417 of Lecture Notes in Computer Science, page 89-102. Springer, (1997)Cameron: High level Language Compilation for Reconfigurable Systems., , , , , and . IEEE PACT, page 236-244. IEEE Computer Society, (1999)An evaluation of medium-grain dataflow code., , and . Int. J. Parallel Program., 22 (3): 209-242 (1994)GPU Accelerated Top-K Selection With Efficient Early Stopping., , and . ADMS@VLDB, page 10-21. (2019)