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Disambiguation of "Fayyazi, Arash"

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CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity.

, , , , and . ISVLSI, page 465-470. IEEE, (2019)

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Afshin Fayyazi

Laila Arash

Haris Arash-Asish

Arash Mehdiani

Arash Alavi

 

Other publications of authors with the same name

Have your QEC and Bandwidth too!: A lightweight cryogenic decoder for common / trivial errors, and efficient bandwidth + execution management otherwise., , , , , , and . CoRR, (2022)ESPRESSO-GPU: Blazingly Fast Two-Level Logic Minimization., , , and . DATE, page 1038-1043. IEEE, (2021)VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology., , , , , and . ISQED, page 224-230. IEEE, (2019)SEERAD: A high speed yet energy-efficient rounding-based approximate divider., , , , , and . DATE, page 1481-1484. IEEE, (2016)qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework., , and . ICCD, page 446-449. IEEE, (2019)Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators., , , and . ISLPED, page 3:1-3:6. ACM, (2022)NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions., , , and . ACM Great Lakes Symposium on VLSI, page 730-735. ACM, (2024)A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning., , , , , and . ACM Great Lakes Symposium on VLSI, page 367-370. ACM, (2019)NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic., , , , , and . FCCM, page 266-267. IEEE, (2021)PEANO-ViT: Power-Efficient Approximations of Non-Linearities in Vision Transformers., , , and . CoRR, (2024)