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How Can We Design Better Networks for DSM Systems?, and . PCRCW, volume 1417 of Lecture Notes in Computer Science, page 171-184. Springer, (1997)FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only)., , , , , , , , , and . FPGA, page 293. ACM, (2010)Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact., , , , , , and . IEEE Comput. Archit. Lett., 9 (2): 49-52 (2010)Exploiting the Benefits of Multiple-Path Network DSM Systems: Architectural Alternatives and Performance Evaluation., and . IEEE Trans. Computers, 48 (2): 236-244 (1999)Simulation of Modern Parallel Systems: A CSIM-based Approach., , , , , , and . WSC, page 1013-1020. ACM, (1997)Impact of Adaptivity on the Behaviour of Networks of Workstations under Bursty Traffic., , , , and . ICPP, page 88-95. IEEE Computer Society, (1998)Reducing Cache Invalidation Overheads in Wormhole Routed DSMs Using Multidestination Message Passing., and . ICPP, Vol. 1, page 138-145. IEEE Computer Society, (1996)EXTENT: a portable programming environment for designing and implementing high-performance block recursive algorithms., , , , , , , and . SC, page 49-58. IEEE Computer Society, (1994)Yield-oriented evaluation methodology of network-on-chip routing implementations., , , , , , , , and . SoC, page 100-105. IEEE, (2009)Evaluating Multi-Level Checkpointing for Distributed Deep Neural Network Training., and . SC (Workshops), page 60-67. IEEE, (2021)