( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.

, , , , , , , , , , , и . FPL, стр. 109-116. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Alec Wodtke

Alec Basson

Céline Alec

Christian Alecke

Jeni Alecu

 

Другие публикации лиц с тем же именем

Quick-Div: Rethinking Integer Divider Design for FPGA-based Soft-processors., , , и . ACM Trans. Reconfigurable Technol. Syst., 15 (3): 32:1-32:27 (2022)Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking., , и . ACM Trans. Reconfigurable Technol. Syst., 15 (4): 43:1-43:33 (2022)Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers through Microbenchmarking., , , и . FPGA, стр. 105-115. ACM, (2021)FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results., , , , , , , , , и 2 other автор(ы). DAC, стр. 1394-1395. ACM, (2022)SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs., , , , , и . ACM Trans. Reconfigurable Technol. Syst., 16 (2): 28:1-28:33 (июня 2023)Rethinking Integer Divider Design for FPGA-Based Soft-Processors., , , и . FCCM, стр. 289-297. IEEE, (2019)Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization., , , , , , , , , и 2 other автор(ы). FPL, стр. 109-116. IEEE, (2022)CHIP-KNN: A Configurable and High-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs., , , и . FPT, стр. 139-147. IEEE, (2020)You Already Have It: A Generator-Free Low-Precision DNN Training Framework Using Stochastic Rounding., , , , , , , , , и 4 other автор(ы). ECCV (12), том 13672 из Lecture Notes in Computer Science, стр. 34-51. Springer, (2022)ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training., , , , , , , , , и 2 other автор(ы). DATE, стр. 1-6. IEEE, (2023)