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TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 798-808 (2019)

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Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems., , , , and . ICSAMOS, page 142-149. IEEE, (2008)SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs., , , , and . RSP, page 102-108. IEEE, (2013)Combined architecture and hardening techniques exploration for reliable embedded system design., , and . ACM Great Lakes Symposium on VLSI, page 301-306. ACM, (2011)TaBit: A framework for task graph to bitstream generation., , , , , and . ICSAMOS, page 201-208. IEEE, (2012)D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems., , , , and . ReCoSoC, page 1-6. IEEE, (2013)ASSURE: RTL Locking Against an Untrusted Foundry., , , , and . CoRR, (2020)Evaluating Static CMOS Complex Cells in Technology Mapping., , and . ARCS Workshops, VDE-Verlag, (2011)Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip., , , , and . CASES, page 3:1-3:10. ACM, (2016)Automatic Generation of Heterogeneous SoC Architectures With Secure Communications., , and . IEEE Embed. Syst. Lett., 13 (2): 61-64 (2021)ASSURE: RTL Locking Against an Untrusted Foundry., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (7): 1306-1318 (2021)