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A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines.

, , , , , и . ICONIP (1), том 9947 из Lecture Notes in Computer Science, стр. 248-255. (2016)

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Takashi Seki

Rolf Morié

Takashi Iwata

Takashi Numaguchi

Takashi Tsuno

 

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A smart imager for the vision processing front-END., , , , и . ASP-DAC, стр. 19-20. ACM, (2000)Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing., , , , и . ICONIP (3), том 8228 из Lecture Notes in Computer Science, стр. 17-24. Springer, (2013)A VLSI Spiking Neural Network with Symmetric STDP and Associative Memory Operation., , , , и . ICONIP (3), том 7064 из Lecture Notes in Computer Science, стр. 381-388. Springer, (2011)Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks., , и . ICONIP (1), том 9947 из Lecture Notes in Computer Science, стр. 240-247. (2016)A Chaotic Boltzmann Machine Working as a Reservoir and Its Analog VLSI Implementation., , , , и . IJCNN, стр. 1-7. IEEE, (2019)Face and arm-posture recognition for secure human-machine interaction., , и . SMC, стр. 411-417. IEEE, (2008)Parameterized digital hardware design of pulse-coupled phase oscillator networks., , , , и . Neurocomputing, (2015)CMOS pulse-modulation circuit implementation of phase-locked loop neural networks., , и . ISCAS, стр. 2174-2177. IEEE, (2008)A Feature Associative Processor for Image Recognition Based on A-D merged Architecture., , , , , , и . VLSI, том 162 из IFIP Conference Proceedings, стр. 77-88. Kluwer, (1999)Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots., , и . ISCAS, стр. 1-. IEEE, (2018)