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Disambiguation of "Chabini, Noureddine"

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Efficient Realization of BCD Multipliers Using FPGAs.

, , , and . Int. J. Reconfigurable Comput., (2017)

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Noureddine Doumi

Noureddine Jaballah

Noureddine Yahi

Noureddine Benkhadda

Adel Noureddine

 

Other publications of authors with the same name

Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers., , , and . SoCC, page 21-24. IEEE, (2006)Two level decomposition based matrix multiplication for FPGAs., , and . ICECS, page 427-430. IEEE, (2009)Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs., , and . ICECS, page 137-140. IEEE, (2011)An improved BCD adder using 6-LUT FPGAs., , and . NEWCAS, page 13-16. IEEE, (2012)Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture., , , and . J. Circuits Syst. Comput., 29 (12): 2050200:1-2050200:23 (2020)Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs., , and . IPDPS Workshops, page 271-277. IEEE, (2011)Optimised realisations of large integer multipliers and squarers using embedded blocks., , , and . IET Comput. Digit. Tech., 1 (1): 9-16 (2007)Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier., , , and . CCECE, page 1-6. IEEE, (2017)FPGA-Based 8x8 Bits Signed Multipliers Using LUTs., and . CCECE, page 366-370. IEEE, (2023)FPGA-Based Digital FIR Filters With Small Coefficients and Large Data Input., and . CCWC, page 218-221. IEEE, (2023)