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Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis., , , , , , and . Int. J. Embed. Real Time Commun. Syst., 2 (3): 1-20 (2011)Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs., , , , , , and . IEEE Embed. Syst. Lett., 11 (3): 93-96 (2019)Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model., , , , and . ACM Trans. Embed. Comput. Syst., 16 (1): 26:1-26:26 (2016)QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL., , , , , , and . CoRR, (2024)Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators., , , , , , and . CoRR, (2020)NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories., , , , , , , , and . CoRR, (2021)A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security., , and . IEEE Des. Test, 39 (2): 90-99 (2022)Retargetable compiler technology for embedded systems - tools and applications., and . Kluwer, (2001)VLSI implementation of LS-SVM training and classification using entropy based subset-selection., , , and . ISCAS, page 1-4. IEEE, (2017)Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem., , , , , and . VEHITS, page 59-69. SciTePress, (2018)