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Disambiguation of "Ciesielski, Maciej J."

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FPGA latency optimization using system-level transformations and DFG restructuring.

, , and . DATE, page 1553-1558. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Christian Ciesielski

Mechthild Ciesielski

Thomas Ciesielski

Axel Ciesielski

Richard Ciesielski

 

Other publications of authors with the same name

Clock period minimization with wave pipelining., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (4): 461-472 (1993)Formal Methods in Arithmetic Circuit Verification: A Brief History and Look into the Future.. DSD, page xxxiv. IEEE, (2023)Placement for Clock Period Minimization With Multiple Wave Propagation., and . DAC, page 640-643. ACM, (1991)High-Level Dataflow Transformations Using Taylor Expansion Diagrams., , , and . IEEE Des. Test Comput., 26 (4): 46-57 (2009)Optimizing data flow graphs to minimize hardware implementation., , , , and . DATE, page 117-122. IEEE, (2009)Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification., , , and . DATE, page 285-289. IEEE Computer Society, (2002)Fast Computation of Data Correlation Using BDDs., , , and . DATE, page 10122-10129. IEEE Computer Society, (2003)Data-flow transformations using Taylor expansion diagrams., , , , and . DATE, page 455-460. EDA Consortium, San Jose, CA, USA, (2007)A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm., , , and . DATE, page 232-236. IEEE Computer Society / ACM, (2000)LPSAT: a unified approach to RTL satisfiability., , and . DATE, page 398-402. IEEE Computer Society, (2001)