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Multi-gigabit-rate clock and data recovery based on blind oversampling., и . IEEE Communications Magazine, 41 (12): 68-74 (2003)Event-driven simulation of Volterra series models in SystemVerilog., , и . CICC, стр. 1-4. IEEE, (2013)Equalizer design and performance trade-offs in ADC-based serial links., , , , , и . CICC, стр. 1-8. IEEE, (2010)Digital Analog Design: Enabling Mixed-Signal System Validation., , , , и . IEEE Des. Test, 32 (1): 44-52 (2015)Simulation and Analysis of Random Decision Errors in Clocked Comparators., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1844-1857 (2009)On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs.. IEEE Trans. Circuits Syst. II Express Briefs, 56-II (6): 449-453 (2009)Adaptive-Bandwidth Phase-Locked Loop With Continuous Background Frequency Calibration.. IEEE Trans. Circuits Syst. II Express Briefs, 56-II (3): 205-209 (2009)Electronic skins for soft, compact, reversible assembly of wirelessly activated fully soft robots., , , , , , , , и . Sci. Robotics, (2018)Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (9): 2096-2107 (2011)A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers., и . IEICE Electron. Express, 16 (13): 20190247 (2019)