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Disambiguation of "Bult, Klaas"

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A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers.

, , and . IEEE Trans. Circuits Syst., 67-II (11): 2322-2326 (2020)

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Walter Klaas

Herbert Klaas

Christoph Klaas

Otmar Klaas

Hendrik Klaassen

 

Other publications of authors with the same name

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration., , and . IEEE J. Solid State Circuits, 50 (7): 1592-1603 (2015)A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers., , and . IEEE J. Solid State Circuits, 53 (7): 1878-1888 (2018)A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 44 (12): 3285-3293 (2009)A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers., , and . ESSCIRC, page 131-134. IEEE, (2017)A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction., , , and . ESSCIRC, page 315-318. IEEE, (2015)A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration., , and . ESSCIRC, page 67-70. IEEE, (2014)A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier., , , , and . IEEE J. Solid State Circuits, 53 (10): 2939-2950 (2018)A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier., , and . IEEE J. Solid State Circuits, 53 (4): 1115-1126 (2018)A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1595-1604 (2013)A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers., , and . IEEE Trans. Circuits Syst., 67-II (11): 2322-2326 (2020)