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Disambiguation of "Deprettere, Ed F."

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Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures.

, , , , , and . ISCAS, page 129-136. IEEE, (1994)

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Ed Robbins

Ed Brost

Efrat Gal-Ed

Jörg Ed Hartge

Ed H. Chi

 

Other publications of authors with the same name

A model for the high-level description and simulation of VLSI networks., , , and . IEEE Micro, 10 (4): 41-48 (1990)A parallel system for photo realistic artificial scene rendering., , , , and . ASAP, page 314-323. IEEE, (1994)On the (Re-)Use of IP-Components in Re-configurable Platforms., , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 264-273. Springer, (2004)Experimental evaluation of different approaches to the multi-pulse coder., and . ICASSP, page 396-399. IEEE, (1984)FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications., and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 1192-1203. Springer, (2006)Pipelined cordic architectures for fast VLSI filtering and array processing., , and . ICASSP, page 250-253. IEEE, (1984)Transforming Signal Processing Applications into Parallel Implementations., , , and . EURASIP J. Adv. Signal Process., (2007)Multiresolution ESPRIT algorithm., , and . IEEE Trans. Signal Process., 47 (6): 1722-1726 (1999)Preface., , and . Des. Autom. Embed. Syst., 7 (4): 303-305 (2002)Converting sequential iterative algorithms to recurrent equations for automatic design of systolic arrays., and . ICASSP, page 2025-2028. IEEE, (1988)