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A data acquisition methodology for on-chip repair of embedded memories., and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 560-576 (2003)A genetic algorithm framework for test generation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 1034-1044 (1997)Compact Test Generation Using a Frozen Clock Testing Strategy., and . J. Inf. Sci. Eng., 16 (5): 703-717 (2000)K2: an estimator for peak sustainable power of VLSI circuits., , and . ISLPED, page 178-183. ACM, (1997)A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults., and . VLSI Design, page 498-505. IEEE Computer Society, (1999)Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation., , and . IOLTW, page 65-. IEEE Computer Society, (2001)Diagnostic Fault Simulation of Sequential Circuits., , and . ITC, page 178-186. IEEE Computer Society, (1992)Enhancing high-level control-flow for improved testability., , and . ICCAD, page 322-328. IEEE Computer Society / ACM, (1996)Use of a field programmable gate array for education in manufacturing test and automatic test equipment., , and . IEEE Trans. Educ., 44 (3): 239-245 (2001)Dynamic state traversal for sequential circuit test generation., , and . ACM Trans. Design Autom. Electr. Syst., 5 (3): 548-565 (2000)