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Disambiguation of "Barragán, Manuel J."

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An oscillation-based test technique for on-chip testing of mm-wave phase shifters.

, , , , , and . VTS, page 1-6. IEEE Computer Society, (2018)

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Hugo Bernal Barragán

Manuel J A Eugster

Manuel J A Eugster

Manuel J A Eugster

Manuel

 

Other publications of authors with the same name

Corrections to "Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge"., , , , , , , , and . IEEE Access, (2023)Guest Editorial: Analog, Mixed-Signal and RF Testing., and . J. Electron. Test., 33 (3): 281-282 (2017)A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs., , , , , , and . J. Electron. Test., 32 (4): 407-421 (2016)A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology., , and . VLSI-SoC, page 1-6. IEEE, (2022)Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique., , , and . LASCAS, page 1-4. IEEE, (2013)A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE., , , , , , , , and . NEWCAS, page 1-5. IEEE, (2023)mm-Wave Single-Pole Double-Throw switches: HBT- vs MOSFET-based designs., , , , , , , and . NEWCAS, page 1-4. IEEE, (2021)Innovative Practices Track: Innovative Analog Circuit Testing Technologies., , , , , , , , , and 8 other author(s). VTS, page 1. IEEE, (2022)A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell., , , and . ISCAS, page 1-5. IEEE, (2023)On-chip reduced-code static linearity test of Vcm-based switching SAR ADCs using an incremental analog-to-digital converter., , , and . ETS, page 1-2. IEEE, (2020)