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Disambiguation of "Andreeva, Valentina"

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Deriving FSM-based tests using $a, b-faults$ for Logic Circuits.

, , , and . ISVLSI, page 80-85. IEEE, (2022)

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Desislava Andreeva

Jana Andreeva

Kalina Andreeva

Andrea Andreeva

Elena Andreeva

 

Other publications of authors with the same name

Test minimization technique for multiple stuck-at faults of combinational circuit.. EWDTS, page 168-170. IEEE Computer Society, (2010)Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults., , , and . EWDTS, page 1-4. IEEE, (2018)ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself., , and . EWDTS, page 1-4. IEEE Computer Society, (2016)Deriving FSM-based tests using $a, b-faults$ for Logic Circuits., , , and . ISVLSI, page 80-85. IEEE, (2022)Deriving Low Power Test Sequences Detecting Robust Testable PDFs., , and . EWDTS, page 1-4. IEEE, (2019)Survivable Discrete Circuits Design., , and . IOLTW, page 13-. IEEE Computer Society, (2002)Fully delay and multiple stuck-at faults testable FSM design., , and . EWDTS, page 1-4. IEEE Computer Society, (2015)A research of heuristic optimization approaches to the test set compaction procedure based on a decomposition tree for combinational circuits., and . EWDTS, page 1-6. IEEE Computer Society, (2013)Finding the shortest transfer sequence of sequential circuit based on simplified ROBDDs., and . EWDTS, page 1-3. IEEE Computer Society, (2017)SAT Solvers Application of Deriving All Test Pairs Detecting Robust Testable PDFs., , and . EWDTS, page 1-4. IEEE, (2021)