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Disambiguation of "Ryu, Kyungho"

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All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (6): 1015-1025 (2018)

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Ryu Yoshiwhara

Hosuk Ryu

Stella Ryu

Ryu Saito

Soojung Ryu

 

Other publications of authors with the same name

An MTJ-based non-volatile flip-flop for high-performance SoC., , , , , and . I. J. Circuit Theory and Applications, 42 (4): 394-406 (2014)MTJ based non-volatile flip-flop in deep submicron technology., , , , , and . ISOCC, page 424-427. IEEE, (2011)A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface., , and . IEEE Trans. Consumer Electronics, 56 (4): 2400-2405 (2010)All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (6): 1015-1025 (2018)ADDLL for Clock-Deskew Buffer in High-Performance SoCs., , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (7): 1368-1373 (2013)A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 181-186 (2012)A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (11): 2044-2053 (2012)All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (3): 1015-1024 (2016)Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (3): 413-421 (2015)Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (10): 2186-2196 (2012)