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Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC.

, , , , and . J. Supercomput., 77 (2): 2124-2137 (2021)

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Online Test of Control Flow Errors: A New Debug Interface-Based Approach., , , , , , and . IEEE Trans. Computers, 65 (6): 1846-1855 (2016)Acceleration of the TSDCE MIMO Channel Estimation Algorithm on a Multi-core Platform., , , , , and . EATIS, page 15:1-15:4. ACM, (2022)Correlation-Based Fingerprint Matching Using FPGAs., , , and . FPT, page 87-94. IEEE, (2005)Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection., , , , , and . IEEE Trans. Computers, 61 (3): 313-322 (2012)Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC., , , , and . J. Supercomput., 77 (2): 2124-2137 (2021)Formal Verification of Fault-Tolerant Hardware Designs., , , , , , and . IEEE Access, (2023)Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study., , , , , , , and . LATW, page 1-6. IEEE, (2011)Exploiting the debug interface to support on-line test of control flow errors., , , , , , and . IOLTS, page 98-103. IEEE, (2013)High performance FPGA-based image correlation., and . J. Real-Time Image Processing, 2 (4): 223-233 (2007)FPGA implementation for an iris biometric processor., , , and . FPT, page 265-268. IEEE, (2006)