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Disambiguation of "Rosinger, Paul M."

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Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.

, , , , and . ISLPED, page 281-286. ACM, (2005)

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Sigurd Rösinger

Lydia Rosinger

Sven Rosinger

Peter Rösinger

Norbert Rösinger

 

Other publications of authors with the same name

Reducing Power Dissipation in SRAM during Test., , , and . J. Low Power Electron., 2 (2): 271-280 (2006)Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (4): 323-335 (2006)Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving., , , , and . DFT, page 477-485. IEEE Computer Society, (2006)Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy., , , , and . ISLPED, page 281-286. ACM, (2005)Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (11): 2502-2512 (2006)Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique., , and . DATE, page 1372-1373. IEEE Computer Society, (2004)Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (7): 1142-1153 (2004)Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving., , , , and . J. Electron. Test., 24 (1-3): 247-257 (2008)Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks., , , and . DATE, page 1647-1652. EDA Consortium, San Jose, CA, USA, (2007)Minimizing test power in SRAM through reduction of pre-charge activity., , , and . DATE, page 1159-1164. European Design and Automation Association, Leuven, Belgium, (2006)