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A formulation for quick evaluation and optimization of digital CMOS circuits., and . ISCAS (6), page 326-329. IEEE, (1999)Split-Gate Logic circuits for multi-threshold technologies., and . ISCAS (4), page 798-801. IEEE, (2001)Logic Design Using EFL Structures.. IEEE Trans. Computers, 25 (9): 952-956 (1976)Pipelined architecture for neural-network-based speech recognition., , and . Neural Parallel & Scientific Comp., 2 (1): 81-92 (1994)Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pump., , and . ISLPED, page 243-248. ACM, (1999)STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (11): 1402-1417 (1992)High-speed dynamic reference voltage (DRV) CMOS/ECL interface circuits., and . IEEE J. Solid State Circuits, 29 (10): 1282-1287 (October 1994)Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime., , and . IEEE J. Solid State Circuits, 30 (6): 629-636 (June 1995)An accurate analytical propagation delay model for high-speed CML bipolar circuits., and . IEEE J. Solid State Circuits, 29 (1): 31-45 (January 1994)A low-power high-performance current-mode multiport SRAM., and . IEEE Trans. Very Large Scale Integr. Syst., 9 (5): 590-598 (2001)