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Testing Computer Hardware through Data Compression in Space and Time., and . ITC, page 83-88. IEEE Computer Society, (1983)Hypergraph Coloring and Reconfigured RAM Testing., and . IEEE Trans. Computers, 43 (6): 725-736 (1994)Modeling Detection Latency with Collaborative Mobile Sensing Architecture., , and . IEEE Trans. Computers, 58 (5): 692-705 (2009)A Data Compression Technique for Built-In Self-Test., , and . IEEE Trans. Computers, 37 (9): 1151-1156 (1988)Correction: IEEE Transactions on Computers 38(2): 320 (1989).Instruction-based delay fault self-testing of pipelined processor cores., , , and . ISCAS (6), page 5686-5689. IEEE, (2005)Analytic modeling of detection latency in mobile sensor networks., , and . IPSN, page 194-201. ACM, (2006)Modified T-Flip-Flop based scan cell for RAS., , , , and . European Test Symposium, page 113-118. IEEE Computer Society, (2010)Analysis and test procedures for NOR flash memory defects., and . Microelectron. Reliab., 48 (5): 698-709 (2008)Efficient Test Set Modification for Capture Power Reduction., , , , , , and . J. Low Power Electron., 1 (3): 319-330 (2005)Delay Fault Testing of Processor Cores in Functional Mode., , , and . IEICE Trans. Inf. Syst., 88-D (3): 610-618 (2005)