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Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures.

, , , and . ISVLSI, page 516-517. IEEE Computer Society, (2007)

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Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores., , , , , and . ISLPED, page 247-252. IEEE/ACM, (2011)Power-efficient implementation of turbo decoder in SDR system., , , and . SoCC, page 119-122. IEEE, (2004)ChipPower: an architecture-level leakage simulator., , , , and . SoCC, page 395-398. IEEE, (2004)Hardware and Software Techniques for Controlling DRAM Power Modes., , , , and . IEEE Trans. Computers, 50 (11): 1154-1173 (2001)Modeling steep slope devices: From circuits to architectures., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Influence of compiler optimizations on system power., , , and . DAC, page 304-307. ACM, (2000)A low latency router supporting adaptivity for on-chip interconnects., , , , and . DAC, page 559-564. ACM, (2005)Design and analysis of an NoC architecture from performance, reliability and energy perspective., , , , and . ANCS, page 173-182. ACM, (2005)Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)., , , , and . FPGA, page 265. ACM, (2005)Editorial., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (1): 1 (2015)