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Automatic Test Generation Using Quadratic 0-1 Programming.

, , and . DAC, page 654-659. IEEE Computer Society Press, (1990)

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Editorial.. J. Electron. Test., 39 (5): 535-536 (December 2023)Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits., , , and . VTS, page 1-7. IEEE, (2022)LSI product quality and fault coverage., , and . DAC, page 196-203. ACM/IEEE, (1981)Defect Diagnosis of Digital Circuits Using Surrogate Faults., and . VDAT, volume 382 of Communications in Computer and Information Science, page 376-386. Springer, (2013)True Minimum Energy Design Using Dual Below-Threshold Supply Voltages., and . VLSI Design, page 292-297. IEEE Computer Society, (2011)A Tuturial on the Emerging Nanotechnology Devices., , and . VLSI Design, page 343-360. IEEE Computer Society, (2004)Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects., , and . ITC, page 375-383. IEEE Computer Society, (2002)Combinational test generation for various classes of acyclic sequential circuits., , and . ITC, page 1078-1087. IEEE Computer Society, (2001)A random access scans architecture to reduce hardware overhead., , and . ITC, page 9. IEEE Computer Society, (2005)SPARTAN: a spectral and information theoretic approach to partial-scan., , , and . ITC, page 1-10. IEEE Computer Society, (2007)