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Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections.

, , , , , , , and . EuroS&P Workshops, page 304-310. IEEE, (2023)

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Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections., , , , , , , and . EuroS&P Workshops, page 304-310. IEEE, (2023)A small and adaptive coprocessor for information flow tracking in ARM SoCs., , , , , , and . ReConFig, page 1-8. IEEE, (2018)JIT Compiler Security through Low-Cost RISC-V Extension., , and . IPDPS Workshops, page 125-128. IEEE, (2023)A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components., , , , , , and . AsianHOST, page 92-97. IEEE, (2018)Gigue: A JIT Code Binary Generator for Hardware Testing., , and . VMIL@SPLASH, page 73-82. ACM, (2023)On The Effect of Replacement Policies on The Security of Randomized Cache Architectures., , , , , , and . CoRR, (2023)A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components., , , , , , and . CoRR, (2018)A small and adaptive coprocessor for information flow tracking in ARM SoCs., , , , , , and . CoRR, (2018)Benchmarking Quantized Neural Networks on FPGAs with FINN., , , and . CoRR, (2021)Porting a JIT Compiler to RISC-V: Challenges and Opportunities., , , , and . MPLR, page 112-118. ACM, (2022)