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An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism.

, , , , and . EUROMICRO, page 1432-1440. IEEE Computer Society, (1999)

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Power consumption reduction scheme focusing on the Depth of Speculative Execution., , , and . CIT, page 207-212. IEEE Computer Society, (2008)Sequential description and parallel execution language DFCII dataflow supercomputers., , and . ICS, page 57-66. ACM, (1991)A priority forwarding scheme for real-time multistage interconnection networks., , , and . RTSS, page 208-217. IEEE Computer Society, (1992)An Architecture of a Data Flow Machine and Its Evaluation., , and . COMPCON, page 486-490. IEEE Computer Society, (1984)The SIGMA-1 dataflow computer., , , , and . FJCC, page 578-585. ACM, (1987)A Control Mechanism of a Lisp-Based Data-Driven Machine., , and . Inf. Process. Lett., 16 (3): 139-143 (1983)Data flow language DFC: Design and implementation., , and . Syst. Comput. Jpn., 20 (6): 1-10 (1989)Dataflow computer development in Japan., , , , and . ICS, page 140-147. ACM, (1990)Evaluation of Associative Memory Using Parallel Chained Hashing., , and . IEEE Trans. Computers, 33 (9): 851-855 (1984)Empirical Study of Latency Hiding on a Fine-Grain Parallel Processor., , and . International Conference on Supercomputing, page 220-229. ACM, (1993)