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Disambiguation of "Taherzadeh-Sani, Mohammad"

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A low-power design methodology for high-resolution pipelined analog-to-digital converters.

, , , and . ISLPED, page 334-339. ACM, (2003)

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Mohammad Sadegh Nurawar Sani

Sadiq Sani

Danial Taherzadeh

Mahmoud Taherzadeh

Werner Sanio

Wege aus der Überschuldung: Nutzung und Nutzen der Schuldnerberatung in individuellen Überschuldungsnotlagen. Uni Mainz, (2009)
 

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A 27 mV output ripple 92% efficiency buck converter using a multi-bit delta-sigma modulator controller and segmented output switch in 180 nm CMOS., , and . ICECS, page 129-132. IEEE, (2016)An analytical approach to the estimation of the spurious-free dynamic range in pipeline A/D converters., , and . ICECS, page 946-949. IEEE, (2003)Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs., and . ISCAS, IEEE, (2006)A pseudo-class-AB telescopic-cascode operational amplifier., , and . ISCAS (1), page 737-740. IEEE, (2004)A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors., , and . VLSI-SOC, page 171-175. IEEE, (2020)An analytical approach to the estimation of dynamic non-linearity parameters in pipeline A/D converters., , and . ESSCIRC, page 715-718. IEEE, (2003)An Analog LO Harmonic Suppression Technique for SDR Receivers., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (1): 182-192 (2019)A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS., , and . ISCAS, page 289-292. IEEE, (2015)A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-µm CMOS convereter read converter., , and . ISCAS (1), page 69-72. IEEE, (2004)A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors., , , and . ICECS, page 217-220. IEEE, (2016)