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Disambiguation of "Mak, Wai-Kei"

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Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design.

, , and . ACM Great Lakes Symposium on VLSI, page 423-428. ACM, (2010)

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Ellen Mak

Rebecca Mak

Kwok Mak

Kei Yoshimoto

Kei Ishii

 

Other publications of authors with the same name

Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration., , and . DAC, page 42:1-42:6. ACM, (2016)SafeChoice: a novel clustering algorithm for wirelength-driven placement., , and . ISPD, page 185-192. ACM, (2010)Clustering based acyclic multi-way partitioning., , and . ACM Great Lakes Symposium on VLSI, page 203-206. ACM, (2003)Temporal logic replication for dynamically reconfigurable FPGA partitioning., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (7): 952-959 (2003)MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (10): 1557-1568 (2013)Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (10): 1652-1663 (2015)I/O placement for FPGAs with multiple I/O standards.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (2): 315-321 (2004)Monte Carlo bounding techniques for determining solution quality in stochastic programs., , and . Oper. Res. Lett., 24 (1-2): 47-56 (1999)Temporal logic replication for dynamically reconfigurable FPGA partitioning., and . ISPD, page 190-195. ACM, (2002)Optimal Buffering of FPGA Interconnect for Expected Delay Optimization., and . FPT, page 289-292. IEEE, (2007)