Author of the publication

Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization.

, and . ATS, page 63-68. IEEE Computer Society, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits., , , , , and . SoCC, page 296-301. IEEE, (2011)IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection., , , and . J. Electron. Test., 23 (4): 341-355 (2007)Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture., , , and . ATS, page 95-100. IEEE, (2007)TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning., , , , , , , and . ITC, page 1-6. IEEE, (2019)Oscillation ring based interconnect test scheme for SOC., , , and . ASP-DAC, page 184-187. ACM Press, (2005)IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults., , , , and . ASP-DAC, page 366-371. IEEE, (2006)De Bruijn graph-based communication modeling for fault tolerance in smart grids., , and . APCCAS, page 623-626. IEEE, (2012)Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator., , and . Asian Test Symposium, page 91-96. IEEE Computer Society, (2013)Test generation for combinational hardware Trojans., , , and . AsianHOST, page 1-6. IEEE Computer Society, (2016)Fast and accurate statistical static timing analysis., , and . ISCAS, page 2555-2558. IEEE, (2014)